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Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025-square
inch post DIP header on the bottom of the board. The bottom side 50-pin header provides access to
the user input/output pins as well as the USB port power output and the module's power input.
The bottom side header mates with a user-supplied, standard, 50-pin, 0.9-inch spaced DIP socket.
Other on-board features include a GPIO-driven LED, SMT footprints for optional external KHz and
MHz crystals and a JTAG/SWD port for connection to Cypress programming and debug tools.
2.0 REFERENCE DESIGN
A reference design comes pre-loaded in the Cypress PSoC ? 5 on the DLP-2232H-PSOC5, and this is
available for download to those who purchase the module. The design was created and compiled
using the free Cypress PSoC Creator? tools. The reference design consists of the following blocks:
It contains the ARM Cortex M-3 CPU along with its internal memory, a USB Interface Block, a User I/0
Block, a Heartbeat Pulse Generator and a Clock Generator. The JTAG Port is used to program and
debug the PSoC ? 5. The ARM core source code is written in C, and uses the compiler included with
the PSoC Creator tm tool. The hardware implemented in the PLD blocks was created using the
Cypress Component Catalog and compiled using the synthesis tool also included in the PSoC
Creator tm tool.
The USB interface captures, interprets and returns command and data information sent from the host
PC through the FTDI USB interface to the PSoC ? 5. Commands include Ping, Flash LED, Set a User
I/O Pin High or Low or Read a User I/O Pin (Section 10 explains these in detail).
The User I/O Block controls access to the 40 user I/O pins accessible through the bottom-side
headers. The User I/O Block can configure these pins as inputs and read their state or as outputs
and drive them high or low.
Rev. 1.0 (February 2012)
3
? DLP Design, Inc.
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